datasheet system peripheral clock source ics650-21 idt? / ics? system peripheral clock source 1 ics650-21 rev h 110409 description the ics650-21 is a low cost, low-jitter, high-performance clock synthesizer for system peripheral applications. using analog/digital phase locked loop (pll) techniques, the device accepts a parallel resonant 25 mhz crystal input to produce up to eight output clocks. the device provides clocks for pci, scsi, fast ethernet, ethernet, usb, and ac97. the user can select one of three usb frequencies and also one of two ac97 audio frequencies. the oe pin puts all outputs into a high-impedance state for board level testing. all frequencies are generated with less than one ppm error, meeting the demands of scsi and ethernet clocking. features ? packaged in 20-pin ssop (qsop) ? available in pb (lead) free package ? lower jitter version of ics650-01 ? operating voltage of 3.3 v or 5 v ? zero ppm synthesis error in all clocks ? inexpensive 25 mhz crystal or clock input ? provides ethernet and fast ethernet clocks ? provides scsi clocks ? provides pci clocks ? selectable ac97 audio clock ? selectable usb clock ? oe pin tri-states the outputs for testing ? selectable frequencies on three clocks ? duty cycle of 45/55 for processor clock and audio clock ? advanced, low-power cmos process ? industrial temperature range available note: eol for non-green parts to occur on 5/13/10 per pdn u-09-01 block diagram clock synthesis circuitry usb clock processor clocks 25 mhz crystal or clock audio clock 20 mhz 3 oe (all outputs) 25 mhz crystal oscillator x1/iclk x2 psel1:0 asel usel vdd 3 2 gnd 2 optional crystal capacitors
ics650-21 system peripheral clock source clock synthesizer idt? / ics? system peripheral clock source 2 ics650-21 rev h 110409 pin assignment usb clock (mhz) processor clock (mhz) audio clock (mhz) 0 = connect directly to ground 1 = connect directly to vdd m = leave unconnected (floating) pin descriptions usel uclk 012 m24 148 13 4 12 5 11 vdd 8 9 10 vdd 20m off/14.318m oe aclk pclk1 17 16 25m 3 x1/iclk vdd pclk3 18 pclk2 1 usel x2 psel0 20 psel1 19 14 2 7 gnd uclk asel gnd 15 6 20-pin (150 mil) ssop psel1 psel0 pclk1 pclk2, 3 00 25 50 0m test mode 01 test mode m0 40 80 m m 33.3333 66.6667 m1 20 40 1 0 20 33.3333 1 m 20 66.6667 1 1 50 100 asel aclk 0 49.152 m 24.576 1 14.318 pin number pin name pin type pin description 1 usel input uclk select pin. determines frequency of usb clock per table above. 2 x2 xo crystal connection. connect to parallel mode 25 mhz crystal. leave open for clock. 3 x1/iclk xi crystal connection. connect to parallel mode 25 mhz crystal or clock. 4 vdd power connect to vdd. must be same value as other vdd. decouple with pin 6. 5 vdd power connect to vdd. must be same value as other vdd. 6 gnd power connect to ground. 7 uclk output usb clock output per table above. 8 20m output fixed 20 mhz output for ethernet. 9 aclk output ac97 audio clock output per table above. 10 25m output fixed 25 mhz reference output for fast ethernet. 11 oe input output enable. tri-states all outputs when low. 12 pclk1 output pclk output number 1 per table above.
ics650-21 system peripheral clock source clock synthesizer idt? / ics? system peripheral clock source 3 ics650-21 rev h 110409 external components the ics650-21 requires a minimum number of external components for proper operation. decoupling capacitor decoupling capacitors of 0.01f must be connected between each vdd and gnd (pins 4 and 6, pins 16 and 14), as close to the device as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock outputs and the loads are over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance) place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . crystal information the crystal used should be a fundamental mode (do not use third overtone), parallel resonant. crystal capacitors should be connected from pins x1 to ground and x2 to ground to optimize the initial accuracy. the value of these capacitors is given by the following equation: crystal caps (pf) = (c l - 6) x 2 in the equation, c l is the crystal load capacitance. so, for a crystal with a 16pf load capacitance, two 20 pf [(16-6) x 2] capacitors should be used. 13 off/14.318m output 14.31818 mhz clock output only when asel = vdd. 14 gnd power connect to ground. 15 asel input aclk select pin. determines fr equency of audio clock per table above. 16 vdd power connect to vdd. must be same value as other vdd. decouple with pin 14. 17 pclk3 output pclk output number 3 per table above. 18 pclk2 output pclk output number 2 per table above. 19 psel0 input processor select pin #0. determ ines frequencies on pclks 1-3 per table above. 20 psel1 input processor select pin #1. determ ines frequencies on pclks 1-3 per table above. pin number pin name pin type pin description
ics650-21 system peripheral clock source clock synthesizer idt? / ics? system peripheral clock source 4 ics650-21 rev h 110409 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics650-21. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature 0 to +70 c note 1: with all clocks at highest frequencies. item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature 0 to +70 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +3.0 +3.3 +5.5 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 5.5 v supply current idd no load, note 1 30 ma input high voltage v ih select inputs, oe 2 v input low voltage v il select inputs, oe 0.8 v output high voltage v oh i oh = -8 ma vdd-0.4 v output high voltage v oh i oh = -8 ma 2.4 v output low voltage v ol i ol = 8 ma 0.4 v short circuit current i os clk output 50 ma input capacitance, inputs except x1 5 pf
ics650-21 system peripheral clock source clock synthesizer idt? / ics? system peripheral clock source 5 ics650-21 rev h 110409 ac electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature 0 to +70 c note 1: values dependent on programming. note 2: measured with 15 pf load. thermal characteristics parameter symbol conditions min. typ. max. units input frequency 25 mhz output clocks accuracy (synthesis error) all clocks 1 ppm output rise time t or 0.8 to 2.0 v, note 2 1.5 ns output fall time t of 2.0 to 0.8 v, note 2 1.5 ns output clock duty cycle uclk, at vdd/2 40 50 60 % pclck, aclck, at vdd/2 45 50 55 % one sigma jitter except aclk 75 ps aclk 120 ps absolute clock period jitter uclk, 20m -500 500 ps power-up time pll lock time from power-up to 1% of final value 14ms parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 135 c/w ja 1 m/s air flow 93 c/w ja 3 m/s air flow 78 c/w thermal resistance junction to case jc 60 c/w
ics650-21 system peripheral clock source clock synthesizer idt? / ics? system peripheral clock source 6 ics650-21 rev h 110409 package outline and package dimensions (20-pin ssop, 150 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information *note: eol for non-green parts to occur on 5/13/10 per pdn u-09-01 parts that are ordered with a ?lf? suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 650r-21* ics650r-21 tubes 20-pin ssop 0 to +70 c 650r-21t* ics650r-21 tape and reel 20-pin ssop 0 to +70 c 650r-21lf ics650r-21l tubes 20-pin ssop 0 to +70 c 650r-21lft ics650r-21l tape and reel 20-pin ssop 0 to +70 c 650r-21i* ics650r-21i tubes 20-pin ssop -40 to 85 c 650r-21it* ics650r-21i tape and reel 20-pin ssop -40 to 85 c 650r-21ilf 650r-21ilf tubes 20-pin ssop -40 to 85 c 650R-21ILFT 650r-21ilf tape and reel 20-pin ssop -40 to 85 c index area 1 2 20 d e1 e seating plane a 1 a a 2 e - c - b .10 (.004) c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.351.75.053.069 a1 0.10 0.25 .0040 .010 a2 -- 1.50 -- .059 b 0.20 0.30 0.008 0.012 c 0.180.25.007.010 d 8.558.75.337.344 e 5.806.20.228.244 e1 3.80 4.00 .150 .157 e 0.635 basic 0.025 basic l 0.401.27.016.050 0 8 0 8
ics650-21 system peripheral clock source clock synthesizer idt? / ics? system peripheral clock source 7 ics650-21 rev h 110409 revision history rev. originator date description of change g p. griffith 02/15/06 added ?power-up time? spec in ac chars. h 11/04/09 added eol note for non-green parts.
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp innovate with idt and accelerate your future netw orks. contact: www.idt.com ics650-21 system peripheral clock source clock synthesizer
|
